1. Home
  2. Research
  3. Publications
  4. Presentation
  5. Group
  6. Department

Personal Details

Designation : Assistant Professor Department : Electrical Engineering E-Mail : adityam@iiserb.ac.in Phone : +91 755 269 1287, 669 1287 Fax :



Academic Details


  • Assistant Professor (July 2016 – Present), Department of Electrical Engineering and Computer Science, Indian Institute of Science Education and Research, Bhopal, India
  • Post-Doctoral Researcher (2014 - 2016), Electrical Engineering and Computer Science Department, University of California, Berkeley, CA, USA
  • PhD in Electrical and Communication Engineering (2008-2014), Indian Institute of Science, Bangalore, India
  • Master of Science in Electrical Engineering (2001-2004), University of Alabama in Huntsville, Huntsville, AL, USA
  • Bachelor of Engineering in Electronics Engineering (1997-2001), University of Mumbai, Mumbai, India

Professional Experience


  • PhD Intern (2011), IMEC (Inter-University Microelectronics Center), Leuven, Belgium
  • Research Assistant (2007-2008), Electrical and Communication Engineering Department, Indian Institute of Science, Bangalore, India
  • Jr. Hardware Design Engineer (2004-2007), PESA Switching Systems Inc.., Huntsville, AL, USA.
  • M.S Intern (2003), Department of Electronic Devices, Linkoping University, Linkoping, Sweden.

    Research Interest


    • Device physics based Analytical/Compact Modeling of futuristic electronic devices with applications to sensors, analog/digital circuit design.

    Publications


    • A. Medury, K. N. Bhat and N. Bhat, “Impact of Carrier Quantum confinement on the Short Channel Effects of Double-Gate Silicon-On-Insulator FINFETs”, Microelectronics Journal Vol.55, September 2016, Pp: 143-151.
    • P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, A. Medury, C. Hu, and Y. S. Chauhan. "BSIM-IMG: Compact model for RF-SOI MOSFETs." In Device Research Conference (DRC), 2015 73rd Annual, pp. 287-288. IEEE, 2015.
    • S. Khandelwal, J. P. Duarte, A. Medury, Y. S. Chauhan, and C. Hu. "New industry standard FinFET compact model for future technology nodes." In VLSI Technology (VLSI Technology), 2015 Symposium on, pp. T62-T63. IEEE, 2015.
    • S. Khandelwal, P. Kushwaha, A. Medury, J. P. Duarte, D. D. Lu, C-H. Lin, M. Dunga, V. Sriramkumar, S. Yao, T. Morshed, N. Paydavosi, S. Jandhyala, Y. S. Chauhan, A. Niknejad and C. Hu. "BSIM-IMG 102.6.0 Independent Multi-Gate MOSFET Compact Model." Technical Manual, 2015.
    • A. Medury, K. N. Bhat and N. Bhat. “Combined Effects of Quantum Confinement and Short-Channel Effects on the Electrostatics of Double-Gate MOSFETs”, IWSPD 2015.
    • S. Khandelwal, J. P. Duarte, A. Medury, Y. S. Chauhan, S. Salahuddin and C. Hu, “Modeling SiGe FinFETs with Thin Fin and Current Dependent Source/Drain Resistance” IEEE EDL. 99, Click Here
    • A. Medury, K. N. Bhat and N. Bhat, “Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate MOSFET” Journal of Applied Physics. 114, 014507-8 (2013); Click Here
    • A. Medury, K. N. Bhat and N. Bhat, “Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor” Journal of Applied Physics. 112, 024513-22 (2012); Click Here
    • A. Medury, K. Mercha, R. Ritzenthaler, A. De Keersgeiter, T. Chiarella, N. Collaert, N. Bhat and K. N. Bhat, “Device Scaling Model for bulk FinFETs” Ultimate Integration of Silicon (ULIS), Grenoble, March 2012, France.
    • A. Medury, N. Bhat and K.N. Bhat, “Temperature dependence of Threshold Voltage for Ultra Thin Silicon Film Symmetric Double-Gate MOSFETs” XVI International Workshop on Physics of Semi- conductor Devices, Dec 2011, Kanpur, India
    • A. Medury, N. Bhat and K.N. Bhat, “A Compact Model incorporating Quantum Effects for Ultra-Thin-Body Double-Gate MOSFETs” International Nanoelectronics Conference (INEC), Hongkong, China, Jan 2010.
    • A. Medury, K.Majumdar, N. Bhat and K.N. Bhat “Ultra-Thin-Body Symmetric Double-Gate MOSFETs: A Perturbation Based Device Model Incorporating Quantization Effects”, XV International Workshop on Physics of Semi-conductor Devices, Dec 2009, New Delhi, India.
    • A. Medury, K.Majumdar, N. Bhat and K.N. Bhat "Modeling theThreshold Voltage of Ultra-Thin-Body(UTB) Long Channel Symmetric Double-Gate (DG) MOSFETs” International Semiconductor Device Research Symposium (ISDRS), Dec 2009, Maryland, USA.
    • A. Medury, I.Carlson, A.Alvandpour and J. Stensby “Structural Fault Diagnostics in Charge-Pump based Phase-Locked Loops”, Proc 18th IEEE International Conference on VLSI Design -2005, Kolkata, India.

2015

Combined Effects of Quantum Confinement and Short-Channel Effects on the Electrostatics of Double-Gate MOSFETs, IWSPD 2015, Bangalore, India.

2010

A Compact Model incorporating Quantum Effects for Ultra-Thin-Body Double-Gate MOSFETs, INEC 2010, Hongkong, China.

    Group


    • Harshit Kansal – PhD student (Joined August 2016)